Referring now to FIG. 1, a low drop-out (LDO) voltage regulator 10 includes an error amplifier 12, a transistor 14, and a voltage divider including resistors R1, R2. An output voltage of voltage regulator 10 is controlled by a feedback connection VFB. A reference voltage VREF and a resistive ratio of resistors R1 and R2 determine the value of the output voltage. Transistor 14 may be a PMOS transistor, which provides the required load current.
A minimum permissible drop out voltage defines the maximum efficiency of the voltage regulator 10. The minimum drop out voltage of voltage regulator 10 is proportional to a minimum overdrive voltage that is required to keep transistor 14 in saturation. Lower drop-out voltages tend to decrease the stability of voltage regulator 10, because a lower drop out voltage requires the use of a larger transistors 14 with both a higher gate parasitic capacitance Cpar and a higher transconductance gm. Larger transistors are also required to accommodate higher maximum load currents, which increases driver amplifier load capacitance Cpar. For example, Cpar may be in the range of 400 pF to 800 pF in this application.
At least two low frequency poles must be considered when the frequency response of voltage regulator 10 is evaluated. One pole is located at output VOUT of voltage regulator 10 and the other pole is located at gate 16 of transistor 14. A phase margin of a feedback loop including error amplifier 12, transistor 14, and voltage divider R1 and R2 can become negative when other parasitic poles are close to two low frequency poles, which may cause the feedback loop to be unstable. The impedance seen from a drain 18 of transistor 14 is high under light load conditions (i.e., relatively large RL) and is inversely proportional to the load current. The output pole is not isolated from the loading conditions.
The output pole cannot be made dominant because it varies widely with the load current through RL (from 0 to 800 mA in this application) and load capacitance CL (from 2 μF up to 100 μF in this application). The situation may worsen if voltage regulator 10 drives a purely resistive load. For example, if the load resistance is 10 ohms and the load capacitance is 2 μF, then the load pole is located at about 8 kHz. Thus, for an open loop gain of 500, the system gain bandwidth will increase to 4 MHz. This gain bandwidth is very high and requires a relatively high current in the error amplifier and/or buffer between it and the pass device. Otherwise, the pole introduced by the capacitance of gate 16 of the transistor 14 will decrease the system phase margin. For load capacitor compensation (external compensation), the loop gain cannot be too high (typically, total voltage regulator 10 open loop gain is around 400 to 500), but lower open loop gain provides correspondingly worse load and line regulation.
Miller compensation can be used to provide increased stability of voltage regulator 10. Referring now to FIG. 2, a driver amplifier 20 with an inner loop or feedback path including Miller capacitor Cm is inserted between output 22 of error amplifier and gate 16 of transistor 14. Driver amplifier 20 is a high bandwidth buffer with low output impedance and a selected gain. Driver amplifier 20 increases the efficiency of Miller compensation by boosting the effective transconductance of transistor 14 to A1gmL, and also helps to overcome the effect of large capacitance Cg at gate 16 of transistor 14 on pole splitting.
Voltage regulator 10A thus has two loops or feedback paths. The first is an outer loop 24 from a positive input 26 of error amplifier 12 to an input 28 of driver amplifier 20 to gate 16 of transistor 14, and closed through drain 18 of transistor 14 and R2. A second, inner loop 30 from VOUT1 to gate 36 of transistor 14 is closed through drain 18 of transistor 14 and Miller capacitor CM. For voltage regulator 10A to be stable, both inner loop 30 and outer loop 24 must be stable.
More particularly, with respect to outer loop 24, the dominant pole at Vout1 is atωP1=1/(r0A1gmLrLCm)  (1)the second pole at Vout is at:ωP2=A1gmL/CL  (2)and the third pole at Vga is at:ωP3=1/(r1Cg).  (3)Miller compensation introduces a zero:ωZm=−A1gmL/Cm.  (4)
There are high frequency poles and zeros in driver amplifier 20. The transfer function from VREF to VOUT is:Av(s)=A0*(1−s/ωZm)/[(1+s/ωP1)(1+s/ωP2)(1+s/ωP3)],  (5)where A0=gm0r0A1gmLrL, is the total open loop gain of the voltage regulator. Let ωu represent the unity gain bandwidth frequency and ωt the gain bandwidth, A0ωd. Then for a two-pole system, the unity gain-bandwidth and phase margin (PM) relationship is:ωu=ωt sin (PM)  (6)orωu=ωP2/tan (PM).  (7)
The zero due to Miller compensation is located at a very high frequency. If it is assumed that the third pole is located at relatively high frequency with respect to the unity gain bandwidth, outer loop 24 can be treated as a two-pole system. The gain bandwidth is written:ωt=A0ωP1=gm0/(2ωCm)  (8)From equations (6) and (8), the unity gain bandwidth is given by:ωu=gm0 sin (PM)/Cm  (9)The relation between second pole position, unity gain bandwidth and phase margin can be obtained from eq. (2), (7) and (9):A1gmL/CL=gm0 sin (PM) tan (PM)/Cm  (10)Thus, the gain of the driver amplifier 20 can be estimated for a given load condition, compensation and load capacitances and loop phase margin.
A high gain bandwidth driver amplifier is needed to maintain a reasonable phase margin of the outer loop. For a given load capacitance CL, doubling the gain of driver amplifier 20 will double the gain bandwidth. The output impedance of driver amplifier 20 must be reduced by half to keep the same phase margin. At the same time all parasitic poles and zeros in driver amplifier 20 must be pushed to higher frequencies.
With respect to inner loop 30 stability, the inner loop has a pole at Vout1:ωP1=1/(r0Cm),  (11)a pole at Vout:ωP2=1/(rLCL),  (12)and a pole at Vga:ωP3=1/(r1Cg)  (13)There is a zero located at zero frequency due to the AC coupling. Since A1 is in inner loop 30, the poles and zeros in driver amplifier 20 are also in inner loop 30. We assume these poles are located at very high frequencies. Because inner loop 30 is AC coupled, it does not participate in any DC activity. The loop gain of inner loop 30 will go up with increasing frequency as a result of the AC-coupling zero. In the frequency range of pole P1, the gain becomes flat. The gain in this frequency range is:A′0=A1gmLrL  (14)Inner loop 30 starts to participate from this point, in the sense that the pole at frequency ωP2 is a dominant pole of inner loop 30. The maximum gain of the inner loop is A′0, which can be reached if pole frequencies ωP1 and ωP2 are sufficiently separated. The gain bandwidth product is:ω′t=A1gmL/CL  (15)Eq. (15) indicates that the gain bandwidth product of inner loop 30 is the second pole of outer loop 24. Higher A1 and gmL, and lower CL make inner loop 30 more difficult to stabilize.
From the analysis of standard Miller compensation, it is known that to make voltage regulators 10 or 10A stable, it is necessary for gain A1 to be high and/or the value of gmL large. At the same time, it is necessary to push the gate pole of transistor 14 to a high frequency, to make the output impedance of driver amplifier 20 low enough. However, it is difficult to design a high gain, low impedance driver amplifier 20 with low power consumption.
Ahuja compensation can be used to increase the stability of inner loop 30. This stability is achieved by pushing the load pole to a higher frequency by the ratio of capacitive gain Ca/Cp, keeping the other pole positions in outer loop 24 unchanged.
Referring now to FIG. 3, there is a dominant pole at Vout1 at a frequency:ωP1=1/(r0A1gmLrLCa)  (16)There is a second pole at Vout at a frequency:ωP2=(Ca/Cp)*A1gmL/CL  (17)There is also a third pole at Vga at a frequency:ωP3=1/(r1Cg)  (18)Ahuja compensation introduces a zero-pole pair, each canceling the other:ωZa, ωPa=gma/Ca  (19)If the high frequency poles and zeros in driver amplifier 20 are ignored, the transfer function of voltage regulator 10B is written:Av(s)=A0/[(1+s/ωP1)(1+s/ωP2)(1+s/ωP3)]  (20)
Similarly to Miller compensation, the third pole due to pass device gate capacitor Cg can be pushed to relatively high frequency. The outer loop gain bandwidth is written:ωt=gm0/Ca  (21)
The gain bandwidth obtained using Ahuja compensation is the same as that obtained using Miller compensation, but the second pole in Ahuja compensation is larger by the ratio of (Ca/Cp). Therefore for the same phase margin, the required gain A1 of driver amplifier 20 can be reduced.
One might hope that the reduction in A1 by capacitive gain would make the design of driver amplifier 20 easier. However, the effects of Ca and Cp on inner loop 30 stability must be taken into account. Referring to a simplified circuit 32 shown in FIG. 4, the transfer function from VIN to VOUT can be written:VOUT/VIN=gmasCa/[(sCa+gma+gdw)(sCp+gup)]  (22)
There are two poles and one zero in this circuit. The zero is located at DC because of AC coupling. One pole is formed by CP and rup, and the other pole is introduced by Ahuja compensation. In the present case, gma>>gdw and gup. From eq. (22), it is apparent that the gain of the circuit represented in FIG. 4 will keep increasing with frequency up to the frequency range of the pole formed by Cp and rup. Thus Cp cannot be made too small, otherwise the gain will be too large, making the loop more difficult to stabilize. If, in a frequency range of interest, SCp>>gup, then eq. (22) can be reduced to:VOUT/VIN=(Ca/Cp)*gma/(sCa+gma)  (23)The same amount of capacitive gain, (Ca/Cp), appears in inner loop 30. Thus, in agreement with the Miller compensation case, the gain bandwidth product of the inner loop is the same as the second pole location of the outer loop. Ahuja compensation creates a new pole in inner loop 30. The new pole is located at:ωa=gma/Ca  (24)
In addition to the load pole and the gate 16 pole of transistor 14, inner loop 30 is a three-pole system. Normally the frequency position of the pole ωa is below that of the gate 16 pole of transistor 14. To have a stable circuit 10B, this pole must either by moved to a higher frequency or be canceled by a zero. To move this pole to a much higher frequency, for example, in the range of 10 to 100 MHz, gma might be made very large. Although making gma larger does, in fact, work in this regard, this approach requires both additional circuits and more power to operate the additional circuits.
In summary, inner loop 30 has a pole at Vout1 at frequency:ωP1=1/(r0Cp),  (25)a pole at Vout:ωP2=1/(rLCL),  (26)a pole at Va:ωP3=gma/Ca,   (27)and a pole at Vga:ωP4=1/(r1Cg).  (28)
As in the Miller compensation case, AC coupling capacitor Ca introduces a zero at zero frequency. There are also poles and zeros in driver amplifier 20 that should be placed at very high frequencies. To make inner loop 30 stable, parasitic capacitance Cp cannot be very small, as it is used to cancel the AC-coupling zero. If Cp is small, inner loop 30 will have high gain in the frequency range of the P1 pole. For a given pole P2 position, the P4 pole has to be placed at a higher frequency, thus making the design of driver amplifier 20 considerably more difficult. Inner loop 30 will be unstable even for relatively small capacitive gain (Ca/Cp) due to the existence of the third pole P3.